1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device of dual gate construction, as well as to a semiconductor device manufactured thereby.
2. Description of the Background Art
In the field of semiconductor devices such as memory devices or logic devices, there have widely been used complementary MOS (CMOS) transistors, each comprising an n-type MOS (NMOS) transistor and a p-type MOS (PMOS) transistor fabricated in a single substrate. In such a CMOS transistor, an area which acts as the gate electrode of an NMOS transistor is arranged so as to become an n-type semiconductor, and an area which acts as the gate electrode of a PMOS transistor is arranged so as to become a p-type semiconductor.
FIGS. 4A to 4D are enlarged cross-sectional views showing a portion of a conventional semiconductor device of dual-gate construction. As shown in FIG. 4A, reference numeral 1 designates a silicon substrate; 2 designates an isolation oxide film; and 3 designates a polysilicon film. In the silicon substrate 1, an active region to be used for fabricating an NMOS transistor and an active region to be used for fabricating a PMOS transistor are formed at both the left side and the right side of the isolation oxide film 2 shown in FIGS. 4A through 4D, although not being illustrated. Within the respective active regions, the polysilicon films 3 are stacked on unillustrated gate insulating films. The polysilicon film 3 is to become a conductive layer of a gate electrode of dual-gate construction. The polysilicon film 3 is divided into an n-type implantation region which is to act as a gate electrode of an NMOS transistor, and a p-type implantation region which is to act as a gate electrode of a PMOS transistor.
FIG. 4A shows the silicon substrate 1 having formed thereon the gate dielectric film and the non-doped polysilicon film 3 when the silicon substrate 1 has been doped for forming a lightly-doped n-type source-drain region and doped for forming a lightly-doped p-type source-drain region. As a result of the silicon substrate 1 being doped, n-type impurities are implanted into the n-type implantation region of the polysilicon film 3, and p-type impurities are implanted into the p-type implantation region of the same.
A sidewall for covering the side surface of the polysilicon film 3 is formed on the surface of the silicon substrate 1 in order to impart a lightly-doped drain (LLD) construction to the NMOS transistor and the PMOS transistor. As shown in FIG. 4B, while a photoresist film 4 covering the p-type implantation region is taken as a mask, impurities are introduced for forming a highly-doped n-type source-drain region.
As shown in FIG. 4C, while a photoresist film 5 covering the n-type implantation region is taken as a mask, impurities are implanted for forming a highly-doped p-type source-drain region. As a result, a highly-doped p-type region 6 containing p-type impurities at high concentration and a highly-doped n-type region 7 containing n-type impurities at high concentration are formed within the polysilicon film 3.
Subsequently, as shown in FIG. 4D, a silicide film 8 is formed on the surface of the highly-doped p-type region 6 and the surface of the highly-doped n-type region 7, in order to decrease the resistance of the gate electrode.
FIGS. 5A to 5d are illustrations for describing a drawback of the above-described conventional method for manufacturing a semiconductor device. As shown in FIGS. 4B and 4C, according to the conventional method, the highly-doped n-type region 7 is formed while the photoresist film 4 is taken as a mask, and the highly-doped p-type region 6 is formed while the photoresist film 5 is taken as a mask. In this case, a gap or overlap may arise between the highly-doped p-type region 6 and the highly-doped n-type region 7 for reasons of an error in the overlay accuracy or dimensional accuracy of a mask used in a photolithography operation.
FIG. 5A shows that the lightly-doped polysilicon film 3 is left in a position between the highly-doped p-type region 6 and the highly-doped n-type region 7 for reasons of an error in the overlay accuracy or dimensional accuracy of a mask. FIG. 5B shows that an overlap arises in a position between the highly-doped p-type region 6 and the highly-doped n-type region 7 for reasons of an error in the overlay accuracy or dimensional accuracy of a mask.
In a case where the silicide film 8 is appropriately formed over the entire surface of the gate electrode as shown in FIGS. 5A and 5B, the resistance of the gate electrode is essentially determined by the silicide film 8 without regard to existence of the lightly-doped polysilicon film 3 or the overlapping area 9. In such a case, an error in the overlay accuracy or dimensional accuracy of a mask does not pose any problem in the characteristic of a semiconductor device.
The silicide film 8 is more likely to be formed in a highly-doped area than in an area of a lightly-doped polysilicon film or in a non-doped area produced by a mask stacking error during formation of a low-concentration region. Such a phenomenon tends to become more noticeable as the pattern of a gate electrode becomes more minute. Even in a case where dust particles are present on the surface of a gate electrode before formation of the silicide film 8, the silicide film 8 will not be formed in the area where the dust particles are present. FIG. 5C shows that no silicide film 8 is formed on the lightly-doped polysilicon film 3, because of the properties of the silicide film 8. FIG. 5D shows that no silicide film 8 is formed in an overlapping area 9 between an n-type region and a p-type region, because the overlapping area 9 is lightly doped as a result of carriers canceling each other.
In these cases, a high-resistance area arises in a gate electrode, which in turn deteriorates the characteristic of a semiconductor device. Conceivably, in the future the interconnection width of a gate electrode will become smaller as miniaturization of a semiconductor device progresses. Therefore, a highly-resistant portion locally arising in a gate electrode poses a greater problem.
The present invention has been conceived to solve such a drawback of the background art and is aimed at providing a method of manufacturing a semiconductor device which prevents a highly-resistant portion from locally arising in a gate electrode of dual-gate construction.
The present invention is also aimed at providing a semiconductor device manufactured by the method.
The above objects of the present invention are achieved by a method of manufacturing a semiconductor device having a gate electrode of dual-gate construction. In the method, there is formed a silicon film which is to act as a conductive layer of the gate electrode. N-type impurities are implanted into a first region of the silicon film. P-type impurities are implanted into a second region of the silicon film. A silicide film is formed on the surface of the silicon film doped with the impurities. Implantation of the n-type impurities and implantation of the p-type impurities are performed such that an overlapping region is inevitably formed between the first and second regions.
The above objects of the present invention are also achieved by a semiconductor device which has a gate electrode of dual-gate construction and is manufactured by the methods described above.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.